1. Field of the Invention
This invention relates to a multilayer interconnection substrate for use in electronic equipment.
2. Disclosure of the Prior Art
In the prior multilayer interconnection substrate, the power interconnection of one layer is connected to the interconnection of another layer with an interconnection position being shifted by using a special circuit riding-on the other layer, as shown in FIG. 1.
As shown in FIG. 1, the first power interconnection 6 is provided with the first layer on the multilayer interconnection substrate, the second power interconnection 7 is provided with the second layer which is positioned on the first layer through the first insulating layer and the third power interconnection 2 is provided with the third layer which is positioned on the second layer through the second insulating layer. Via holes 1 which connect the first power interconnection 6 to the second power interconnection 7 are provided with the first insulating layer and via holes 3 which connect the second power interconnection 7 to the third power interconnection 2 are provided with the second insulating layer, the position of the via holes 1 being shifted from that of the via holes 3.
Also, FIG. 2 shows a partial sectional view of the prior multilayer interconnection substrate, in which there are used the power interconnections which are formed in such a manner that the via holes pass through the lower layer to the upper layer at the same position. As seen from FIG. 2, a reference number 20 indicates a ceramic or glass ceramic multilayer interconnection substrate, 24 is the first insulating layer, 25 is the second insulating layer, 26 is the first power interconnection, 27 is the second power interconnection and 22 is the third power interconnection. The first power interconnection 26, the second power interconnection 27 and the third power interconnection 22 are connected through the via holes each other.
In the prior multilayer interconnection substrate as shown in FIG. 1, with respect to the power interconnection, there are problems that area of the power interconnection is extended and thus the resulting distribution resistance causes a higher voltage drop, that a pattern density is lowered and that open circuits occur when via contact fails.
In addition, in the prior multilayer interconnection substrate as shown in FIG. 2, it is possible to solve the problem of the high voltage drop in the power interconnection but the via holes will become deeper. Therefore, there is problem that, in a resist process for forming the power interconnection, the resist largely remains in the via hole portion when the depth of the via hole portion is beyond 30 microns and thus all the resist cannot be removed resulting in a in the residual resist 38, as shown in FIG. 3. In FIG. 3, a reference number 30 is a ceramic or glass ceramic multilayer interconnection substrate, 34 is the first insulating layer, 35 is the second insulating layer, 33 is the third insulating layer, 36 is the first power interconnection, 37 is the second power interconnection, 32 is the third power interconnection and 31 is the resist.
Moreover, there is known a flatting method using a embedding process but there are defects that the number of steps in the process is increased and connecting resistance is raised.